Development of Low-cost Wafer Level Package through Integrated Design and Simulation Analysis
Wafer level package (WLP) provides the smallest form factor to satisfy multifunctional device requirements along with improved signal integrity for todays latest handheld electronics. WLP with various design configurations is fast becoming a common package for high performance applications. Besides large-die or embedded WLPs in System-in-Package, technology development in the industry also focuses on cost-effective WLP with acceptable level of functional and reliability performances, suitable for low-pin-count or small-die applications. Nepes is developing a series of low-cost wafer level packages (LCWLPs) to address the cost and technology demands. This paper will focus on prototyping of a non-UBM LCWLP with RDL, to be used as a baseline for relative cost, functional and reliability performances comparison with conventional WLPs and future LCWLPs of the same die sizes and ball layout. Three sizes of LCWLP are designed and simulated, prior to assembly and reliability tests. The structural design features electrical, mechanical and thermal simulations of LCWLP with three chip sizes and ball layout. Simulation results show LCWLPs investigated are able to satisfy the functional and reliability requirements. Electrical simulation demonstrates that LCWLP with the same I/O counts but smaller package size, has better functional performance than FCBGA. Mechanical simulation indicates that wafer level warpage of all LCWLPs studied are within acceptable range for wafer level processes. For board level reliability, LCWLPs are expected to pass the thermal cycling test. Furthermore, LCWLPs are small in sizes with very low junction-to-case thermal resistance, able to keep the maximum junction temperature low and cool the chips during operations. Its thermal performance is strongly influenced by the chip size but independent of the Cu RDL density.
Tong Yan Tee Germaine Hoe Shan Gao Glen Siew Haoyang Chen Serine Soh In Soo Kang Jong Heon Kim Teck Kheng Lee Bok Leng Ser Hun Shen Ng
Nepes Pte Ltd.12 Ang Mo Kio Street 65, Singapore 569060. Institute of Microelectronics.11 Science Park Road, Singapore Science Park II, Singapore 117685. Institute of Technical Education.201 Circuit Road, Singapore 379498. SMARTS Technology LLP.Blk 425, Canberra Road, #11-477, Singapore 750425.
国际会议
上海
英文
549-555
2011-08-08（万方平台首次上网日期，不代表论文的发表时间）