The fatigue failure analysis of 3D SiP with Through Silicon Via

摘要：

Three-dimensional (3D) die stacking based on the Through Silicon Via (TSV) is a promising new packaging technology for its high performance, multi functionality, relatively smaller chip size and lower cost etc. However, the application of TSV in 3D SiP will introduce lots of new problems regarding the reliability, such as thermal stress, deformation, fatigue failure In this study, the thermal-mechanical reliability of a TSV-enabled 3D chip stack is simulated with FEA. Various design parameters are discussed regarding the system reliability: the number of stacked chips, the thickness of stacked chips, interposer, the diameter of TSV and the micro bump, the height of micro bump and the distance between the TSV.

作者: Wenping Kang Yang He Zhiyuan Zhu Min Miao Jing Chen Yufeng Jin

作者单位: National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij

会议类型: 国际会议

会议名称: 2011 12th International Conference on Electronic Packaging Technology & High Density Packaging(2011 电子封装技术与高密度封装国际会议)

会议地点: 上海

会议语种:英文

页码: 637-640

在线出版日期: 2011-08-08（万方平台首次上网日期，不代表论文的发表时间）