3D Silicon-Based Packaging for Light Emitting Diodes
The three-dimensional (3D) light-emitting diodes (LEDs) integration package based on silicon with through silicon vias (TSV) attracts a lot of attention because of a better performance, lighter package, and higher integration density. Two main kinds of LED chip including conventional chip (CC) and vertical chip (VC) encapsulated in silicon platform with and without a reflector cup are analyzed through simulation to understand the optical and thermal characteristics of the module. The results show that the light extraction efficiency (LEE) is more dependent on the type of the chip instead of the structural parameters of the reflector cup. However, it has a significant effect on the far-field pattern of the package module. The thermal analyses show that the temperature distribution is uniform due to the high thermal conductivity and convection coefficient. Mismatch of thermal expansion coefficients (CTE) between TSV-full-filled copper of 100um-thickness and silicon causes large thermal stress, the maximum von Mises stress reaching 272MPa, which would be decreased by 11.0% through half filling TSV with the copper of 20um-thickness.
Bin Cao Shan Yu Huai Zheng Sheng Liu
School of Optoelectronic Science and Engineering, Huazhong University of Science and Technology, Wuh Division of MOEMS, Wuhan National Laboratory for Optoelectronics, Huazhong University of Science and School of Optoelectronic Science and Engineering, Huazhong University of Science and Technology, Wuh
国际会议
上海
英文
1090-1093
2011-08-08（万方平台首次上网日期，不代表论文的发表时间）