Design and Implementation of an Efficient Montgomery Modular Multiplier with a New Linear Systolic Array

摘要：

Abstract桾o resolve the latency problem of implementing Montgomery modular multiplication algorithm using the linear systolic array, this paper proposes the improved Montgomery algorithm, and improves the systolic array by combining the long carry save adder (CSA) structure. This paper also proposes a series of methods to optimize the critical path and a non-waiting modular multiplication strategy which can allow the exponentiator to ignore the output delay of the multiplier. At last, the new modular multiplier can provide a much higher calculation speed, and also can avoid the signal broadcasting and amplification problem of the long CSA structure. The verification prototype is built on the FPGA. The time for 1024-bit modular multiplication merely needs 4.75..s under clock frequency of 243.9 MHz.

作者: Jizhong Liu Jinming Dong

作者单位: School of software Beihang University Beijing, China School of Electrical Engineering Beihang University Beijing, China

会议类型: 国际会议

会议名称: 2010 IEEE International Conference on Information Theory and Information Security(2010 IEEE 国际信息论与信息安全会议)

会议地点: 北京

会议语种:英文

页码: 225-229

在线出版日期: 2010-12-17（万方平台首次上网日期，不代表论文的发表时间）