Implementation of 20Gbit/s area-optimization DQPSK precoder employing FPGA

摘要：

In this paper, a new model based on an ameliorated Brent Kung (BK) parallel prefix network (PPN) algorithm was proposed and realized in Virtex V FPGA. In the implementation, compute complexity (area) optimization was achieved. 770 slice registers was utilized and which saved 60% logic resources to the before algorithm.

作者: Liming Zhou Mi Lin Yangan Zhang Gai Wang Minglun Zhang Jinnan Zhang Xueguang Yuan Yongqing Huang

作者单位: Key Laboratory of Information Photonics and Optical Communications (BUPT), Ministry of Education, Beijing, 100876, China Institutes of Information Photonics and Optical Communications (BUPT), P.O.Box 66, Beijing, 100876, China

会议类型: 国际会议

会议名称: Asia Communications and Photonics Conference and Exhibition(2010亚洲光纤通信与光弹博览会及研讨会 ACP 2010)

会议地点: 上海

会议语种:英文

页码: 391-392

在线出版日期: 2010-12-08（万方平台首次上网日期，不代表论文的发表时间）