Single Chip Design of Closed-loop Class D Audio Power Amplifier

摘要：

A single chip design of class D audio power amplifier is presented. It is composed with a rail-to-rail operational amplifier and a closed-loop pulse width modulation. It achieves a maxim power of 3.75W and consumes about 1.9mA quiescent current as maxim efficiency is more than 90%. When sine wave input signal frequency is 1KHz and output power is 3.75W, the THD of output signal is only 0.1%. The chip is designed with thermal protection which turns the device off when the junction temperature surpasses 150℃ to prevent damage to the IC.

作者: XU Yong ZHAO Fei WU Yuanliang MIN Rui SUN Zheng TANG Lu

作者单位: College of Sciences, PLA University of Science and Technology, Nanjing 211101, CHN Institute of Command Automation, PLA University of Science and Technology, Nanjing 210007, CHN Institute of RF-& OE-ICs, Southeast University, Nanjing, 210096, CHN

会议类型: 国际会议

会议名称: 2010年无线通信与信号处理国际会议

会议地点: 上海

会议语种:英文

页码: 1-5

在线出版日期: 2010-10-20（万方平台首次上网日期，不代表论文的发表时间）