Low Power IEEE 802.15.4a UWB Digital Rx Baseband Architecture
This paper presents a low power ultra-wide band digital receiver baseband architecture for handling IEEE 802.15.4a packets in real-time. Real-time processing allows duty cycling of the analog frontend, which is key to achieve low power consumption. The architecture consists of a programmable application specific instruction set processor and a set of application specific integrated circuits. The design is split up into multiple clock domains to meet timing requirements of up to 499.2MHz. The architecture runs in real-time on FPGA, and is synthesizable for 90nm CMOS at 0.84V. This results in a low power flexible C programmable baseband architecture, which is ideal for algorithm development and tuning.
Michael De Nil Ben Busze Alex Young Dries Neirynck Hans Pflug
Kathleen Philips, Jos Huisken, Jan Stuyt and Harmke de Groot Holst Centre / imec High Tech Campus 31 Kathleen Philips, Jos Huisken, Jan Stuyt and Harmke de Groot Holst Centre / imec High Tech Campus 31
国际会议
南京
英文
1-4
2010-09-20(万方平台首次上网日期,不代表论文的发表时间)