A 90nm CMOS 5-bit 2GS/s DAC for UWB Transceivers
A 5-bit 2GS/s current-steering D/A converter for ultra-wideband (UWB) transceivers is presented in this paper. It is based on a full-binary weighted architecture and achieves better than 10-bit static linearity without calibration. The DAC occupies 0.5mm× 0.75mm in a standard 90nm CMOS technology. A spurious-free dynamic range (SFDR) of more than 30dB has been measured over the complete Nyquist interval at sampling frequencies of 2GS/s. The power consumption at a 2GHz clock frequency for a near-Nyquist sinusoidal output signal equals only 12mW. For UWB signals, which have about 500MHz bandwidth, the DAC consumes even less than 8mW.
Xu Wu Michiel Steyaert
ESAT-MICAS, Katholieke Universiteit Leuven Heverlee 3001, Belgium
国际会议
南京
英文
1-4
2010-09-20（万方平台首次上网日期，不代表论文的发表时间）