A research of high-speed Batchers odd-even merging network

摘要：

Batchers odd-even merging network can be easily implemented on hardware. And its parallel working between the comparator is very beneficial to play the advantages of hardware such as high efficiency and high speed. These make it as the most widely used sort algorithm. In this paper, FPGA is used to implement Batchers odd-even merging network, solving the problems of traditional design. And the scalability of Batchers odd-even merging network is also studied in this paper. The end results show that Batchers odd-even merging network can be used to not only sort and classify the data, but also fast complete the parallel data packets distribute.

作者: Yang Jun Li Na Ding Jun Guo Yixiong Tang Zuoxia

作者单位: School of Information Science and Engineering, Yunnan University Kunming, China

会议类型: 国际会议

会议名称: 2010 International Conference on E-Health Networking,Digital Ecosystems and Techonlogies(2010电子健康网络、数字生态系统和技术国际会议 EDT 2010)

会议地点: 深圳

会议语种:英文

页码: 77-80

在线出版日期: 2010-04-17（万方平台首次上网日期，不代表论文的发表时间）