FPGA-based multi-channel CRC generator implementation

摘要：

This article mainly describes a way of designing a parallel and highly pipelined Cyclic Redundancy Code (CRC) generator. The design can handle five different channels at an input rate of 2Gbps each. The generated CRCS are compatible with the 32-bit Ethernet standards. This circuit has been implemented with the chip EP2C35F672C6 of ALTERA using the properties of Galois Field. The synthesis results show that the design can meet the needs of high-speed data integrity check.

作者: Yang Jun Ding Jun Li Na GuoYixiong Dong Yin

作者单位: School of Information Science and Engineering, Yunnan University Kunming, China

会议类型: 国际会议

会议名称: 2010 International Conference on E-Health Networking,Digital Ecosystems and Techonlogies(2010电子健康网络、数字生态系统和技术国际会议 EDT 2010)

会议地点: 深圳

会议语种:英文

页码: 81-84

在线出版日期: 2010-04-17（万方平台首次上网日期，不代表论文的发表时间）