An FPGA implementation of Dynamic Reconfigurable Lifting-Based Wavelet Packet Processor for Real-Time Scalable Audio Coding
In this paper, dynamic algorithm transforms (DAT) for reconfigurable real-time processor for audio appli-cation based on the adaptive wavelet packet (WP) de-composition are presented. DAT techniques is to con-strain a minimum cost sub-band decomposition of wavelet transform by maximinimizing the minimum masking threshold (which is limited by the perceptual entropy) in every sub-band for the given embedded processor architecture and temporal resolution. The processor architecture is based on the implementation of the wavelet transform by means of its factoring into lifting steps. Practical reconfiguration strategies for the given processor are presented.
Alexey Petrovsky Maxim Rodionov Wanggen Wan Alexander Petrovsky
Department of Computer Engineering, Belarusian State University of Informatics and Radioelectronics School of Communication and Information Engineering, Shanghai University
国际会议
上海
英文
1624-1630
2010-10-20(万方平台首次上网日期,不代表论文的发表时间)