Electrical characterization of sidewall insulation layer of TSV
This paper presented a method to examine the electrical characteristics of sidewall insulation layer of through silicon via (TSV), including breakdown voltage and sidewall capacitance. Blind via samples were fabricated for the experiment using deep reactive ion etching. 2μm SiO2 insulation layer was deposited using PECVD (Plasma enhanced chemical vapor deposition). Ti/W/Cu adhesive/barrier/seed layer was sputtered, and then copper was electroplated to fill vias. The final blind via sample was a MOS capacitor-like structure. To measure the electrical characteristics of the sidewall insulation layer, I-V and C-V test were implemented. As a result, the breakdown voltage of TSV sidewall insulation layer was about 40V, calculated breakdown electrical field strength of oxide layer was about 100V/μm. C-V test result showed a capacitance of about tens of femto-farads (fF), while substrate parasitic capacitance affected the measured capacitance greatly. Calculation and simulation of via capacitance were also carried out, and the capacitance of sidewall insulation layer was about 1pF in our experiment.
Xin Sun Ming Ji Shenglin Ma Yunhui Zhu Wenping Kang Min Miao Yufeng Jin
National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij
国际会议
西安
英文
77-80
2010-08-16（万方平台首次上网日期，不代表论文的发表时间）