A Stress Relief Method for Copper Filled Through Silicon Via with Parylene on Sidewall

摘要：

Though silicon via (TSV) with parylene layer has many advantages, such as low temperature, CMOS matched lowtemperature process and so on. In this paper, we use parylene layer as the sidewall to relieve the thermal stress in TSVs. Thermo-mechanical simulation of TSVs is performed to disscuss the effect of the parylene layer. It is found that the introduction of parylene layer can reduce the thermal stress in TSV, and this improvement tends to be larger when it is closer to the practical situation. We also discuss the effects of the temperature, the parylene thickness and the diameter of via on thermal stress distribution in TSVs. And it is indicated that as the parylene thickness increased, the thermal stress in TSVs decreased.

作者: Wenping Kang Maosheng Zhang Yunhui Zhu Shenglin Ma Min Miao Yufeng Jin

作者单位: National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij Information Microsystem Research Institute, Beijing Science and Information Technology Institute, Be National Key Laboratory of Science and Technology on Micro/Nano Fabrication, Peking University, Beij Shenzhen Graduate School of Peking University Information Microsystem Research Institute, Beijing Sc

会议类型: 国际会议

会议名称: 2010 11th International Conference on Electronic Packaging Technology & High Density Packaging(2010 电子封装技术与高密度封装国际会议)

会议地点: 西安

会议语种:英文

页码: 98-101

在线出版日期: 2010-08-16（万方平台首次上网日期，不代表论文的发表时间）