Prediction of package warpage combined experimental and simulation for four maps substrate
As electronic devices become lighter, thinner, shorter, and smaller, IC packages follow. Low-profile type packages are reduced in thickness, so the stiffness of thin type packages is weaker due to the thermo-mechanical effects of manufacturing processes, testing, and operations. Due to the different temperatures in those processes, and the differences in coefficient thermal expansion (CTE) of each material, the mismatch of material properties induces package warpage and stress distribution. Both of these phenomena will change the package outline, in turn generating passivation cracks, pattern shift, loose bond balls, wire breakage, voids, buckling, hillocks, delamination, and/or de-bonding. Consequently, the reliability of microelectronic packages will be decreased and assembly quality lowered. Sequential processing models of packages were built to simulate package warpage and stresses after the post mold curing (PMC) and reflow processes. The package warpage was measured by the surface and flatness measurement system to verify the accuracy of the simulation results. In other words, we compared the warpage differences between simulation data and package warpage data acquired by a surface and flatness measurement system to confirm whether the simulation model was reliable or not. If the simulation result was not close to actual package warpage, the simulation model was adjusted to bring the simulation results closer to the actual package warpage data. This research investigated the warpage and stress distribution by the finite element method. The affected factors are as below: 1. compound materials; 2. chip size; and 3. chip thickness. After that, a full factorial design of experiment (DOE) was arranged, with a base of eight runs, to determine which factor was the key by means of statistical software (Minitab), and an optimal package design was arranged. The effect of the molding compound was determined to be more important than either chip size or chip thickness.
R. W. Wu C. K. Chen Lung-Chuan Tsao
NXP Semiconductors, Taiwan, China Department of Materials Engineering, Pingtung University of Science & Technology, Taiwan, China
国际会议
西安
英文
576-581
2010-08-16（万方平台首次上网日期，不代表论文的发表时间）