Drop Test Simulation of 3D Stacked-Die Packaging with Input-G Finite Element Method

摘要：

Transient responses of 3D stacked-die package with through silicon via (TSV) structure under board level drop test load following the JEDEC standard are investigated using the Input-G finite element simulation method. In order to reduce the finite element mesh size the stacked-die package under investigation is modeled with details while the others are simplified as blocks with equivalent material properties. The deflection and velocity responses of the stacked-die package located at center of test board are obtained. The stress and strain of the copper via, and micro solder pumps and silicon dies are checked and compared. The simulation results show that the critical position is located at the corner of bottom layer of copper via, copper pad and micro solder bumps. The logarithmic strain evolutions of critical copper pad and micro solder bump are investigated.

作者: Zhaohui Chen XueFang Wang Yong Liu Sheng Liu

作者单位: Research Institute of Micro/Nano Science and Technology, Shanghai Jiao Tong University, Shanghai, P. Wuhan National Lab for Optoelectronics, Huazhong University of Science & Technology, Wuhan, P.R. Chi Wuhan National Lab for Optoelectronics, Huazhong University of Science & Technology, Wuhan, P.R. Chi Research Institute of Micro/Nano Science and Technology, Shanghai Jiao Tong University, Shanghai, P.

会议类型: 国际会议

会议名称: 2010 11th International Conference on Electronic Packaging Technology & High Density Packaging(2010 电子封装技术与高密度封装国际会议)

会议地点: 西安

会议语种:英文

页码: 742-746

在线出版日期: 2010-08-16（万方平台首次上网日期，不代表论文的发表时间）