The Effect of Microvia-In-Pads Design on SMT Defects in Ultra-Small Component Assembly
High Density Interconnect (HDI) and micro-via in pads technologies continue to facilitate the development of smaller, lighter, more powerful electronics by enabling finer pitch I/Os, thinner circuit boards, and higher routing densities. However, increases in Printed Circuit Boards (PCBs) density and the need for higher electrical performance have resulted in several design challenges. Some of these unique challenges for both PCB fabricators and assemblers are related to the micro-via in pads to the organic integrated circuit (IC) substrate. On the assembly side, chronic SMT defects with conventional micro-via in pads are the high occurrence of tombstoning and considerable voiding that can lead to low yields and increased product costs. Although tombstoning and voiding in typical solder joints have been studies extensible, very little work has been done on the emerging micro-via applications which appear to be more prone to tombstoning and voiding problems. In this study, tombstoning behavior was primarily studied and potential factors such as micro-via in pads structure, reflow profile, reflow atmosphere, solder paste and paste deposit volume which may affect tombstoning in micro-via of lead-free solder joints were investigated.
Yong-Won Lee Keun-Soo Kim Katsuaki Suganuma
Manufacturing Technology Center, Samsung Electronics Co., Ltd.416, Maetan 3-dong, Yeongtong-gu, Suwo Institute of Science and Industrial Research, Osaka University Mihogaoka 8-1, Ibaraki, Osaka 567, Ja
国际会议
西安
英文
870-875
2010-08-16（万方平台首次上网日期，不代表论文的发表时间）