A Package Method for Reducing Bus Crosstalk in Full Chip ESD Protection Circuit

摘要：

In this paper, a package method that can be applied to the full-chip electrostatic discharge (ESD) protection circuit is presented. By connecting ESD protection circuit bus, power clamp circuit bus and core circuit bus to the conductor layer of package substrate, the bus of each module in internal chip will be independent respectively, so that it can reduce the bus crosstalk effect of core circuit that is induced by ESD pulse that are discharged from ESD protection circuit, and improve the robustness of chip. The method that power clamp circuit bus connect to the conductor layer of package substrate can not only reduce the parasitic resistance of the bus, but also improve the protect efficiency of the individual power clamp circuit and reduce the quantity of the power clamp circuit and the area of chip.

作者: Zhang Bing Chai Chang-chun Yang Yin-Tang

作者单位: Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xian 710071, China

会议类型: 国际会议

会议名称: 2010 11th International Conference on Electronic Packaging Technology & High Density Packaging(2010 电子封装技术与高密度封装国际会议)

会议地点: 西安

会议语种:英文

页码: 1183-1185

在线出版日期: 2010-08-16（万方平台首次上网日期，不代表论文的发表时间）