Model of N-Type Polycrystalline Silicon Thin Film Transistors Under DC Bias Stress

摘要：

The density of trap states distribution in the bulk of polycrystalline silicon thin film transistor is modeled by constant deep states and exponential tail states. Pao-Sah method is used to model the hot carrier degradation behavior. At low gate voltage bias stress, tail states increase with the stress time, which indicates the generation of local strain bonds near the drain. At higher gate voltage bias states, both deep states and tail states increase with the stress time, which indicates the generation of both dangling bonds and local strain bonds near the drain. Transfer characteristic degradation with stress time is calculated. The results are agreed with the available experiment data successfully.

作者: Hongyu He Xueren Zheng

作者单位: Faculty of Physics and Optoelectronic Engineering Guangdong University of Technology, Guangzhou 5100 Institute of Microelectronics, School of Electronic and Information Engineering South China Universi

会议类型: 国际会议

会议名称: 2010 11th International Conference on Electronic Packaging Technology & High Density Packaging(2010 电子封装技术与高密度封装国际会议)

会议地点: 西安

会议语种:英文

页码: 949-952

在线出版日期: 2010-08-16（万方平台首次上网日期，不代表论文的发表时间）