RELIABILITY SIMULATION OF METAL BUMP IN A THREE-DIMENSIONAL CHIP STACKING STRUCTURE

摘要：

In order to adapt the development of the Integrated circuit, a three-dimensional chip stacking structure was developed to achieve high performance, low power consumption and small packaging size. The 3D structure was divided into four major parts, including through silicon via, isolation wall, conductive line, and metal bump. We focused on the reliability of the metal bump in this kind of three-dimensional chip stacking structure. However, the strain and the stress were difficult to be detected during the temperature cycling. Simulating and analyzing with the software ANSYS was an appropriate method. In this paper, we used the software ANSYS to simulate and analyze this 3D chip stacking structure in order to find out the dangerous point during the temperature cycling.

作者: Zhou Zhang Yuliang Deng Yunlong Liu Yufeng Jin

作者单位: Shenzhen Graduate School of Peking University, Shenzhen 518055, China;Shenzhen State Microelectronic Shenzhen State Microelectronics Co. LTD, Shenzhen, 518057, China Shenzhen Graduate School of Peking University, Shenzhen 518055, China;National Key Laboratory on Mic

会议类型: 国际会议

会议名称: 2010 11th International Conference on Electronic Packaging Technology & High Density Packaging(2010 电子封装技术与高密度封装国际会议)

会议地点: 西安

会议语种:英文

页码: 1218-1220

在线出版日期: 2010-08-16（万方平台首次上网日期，不代表论文的发表时间）