High Parallel Disparity Map Computing on FPGA

摘要：

In this paper we present a method for disparity map computing and its correspondent high parallel hardware accelerator. Our solution considers a two step processing algorithm. First, we compute a one-dimensional biased sum of absolute differences, and later a spurious removal technique is performed to eliminate wrong estimations. The hardware accelerator introduces a memory organization, an address generation scheme and data-path units that have scalable features for several resolutions, frame rates, silicon use, and power consumption instantiations. We have implemented a five stage pipelined organization that operates at 174.5 MHz over an VIRTEX II PRO 2vp30fg676-7 FPGA device, carries out an equivalent of 9.074 GOPS and processes 142 frames per second of Common Intermediate Format (CIF).

作者: Humberto Calderón Jesùs Ortiz Jean-Guy Fontaine

作者单位: Italian Institute of Technology TEleRobotics & Applications (TERA) Dept. Via Morego, 30, 16163 Genoa, Italy

会议类型: 国际会议

会议名称: 2010 IEEE/ASME International Conference on Mechatronic and Embedded System and Applications(2010 IEEE 机电一体化和嵌入式系统与应用国际会议)

会议地点: 青岛

会议语种:英文

页码: 307-312

在线出版日期: 2010-07-15（万方平台首次上网日期，不代表论文的发表时间）