A New Full Adder Design For Tree Structured Arithmetic Circuits

摘要：

A new low power and high speed full adder is designed which targets at tree structured applications. By employing complementary signal at input,buffer inverter at output,a new transmission gate based full adder is proposed. This new adder uses 20 transistors to achieve high driving ability and low power consumption. Simulation in Semiconductor Manufacturing International Corporation 0.18-um CMOS process indicates that the new adder outperforms the four existing adders in terms of power delay product. The design has a full voltage swing,making it suitable for technology scaling. The adder can be used for highperformance circuits such as high speed and low power multipliers.

关键词： full adder:multiplier:low power:high speed

作者: Jian-Fei Jiang Zhi-Gang Mao Wei-Feng He Qin Wang

作者单位: School of Microelectronics Shanghai Jiao Tong University Shanghai,China

会议类型: 国际会议

会议名称: 2010 2nd International Conference on Computer Engineering and Technology(2010年第二届计算机工程与技术国际会议 ICCET 2010)

会议地点: 成都

会议语种:英文

页码: 2351-2354

在线出版日期: 2010-04-16（万方平台首次上网日期，不代表论文的发表时间）