Research on the Problems of Satellite Borne FPGA Based Finite State Machine
The FPGA design tools now wildly used would optimize finite state machine’s encoding style and circuit automatically to achieve better performance on timing and area, which made finite state machine full of potential dangerous for space applications. This paper propounded some design methods such as redundancy the state flip-flops and brought in third-part design tool in FPGA design flows to conquer the limitation of design tools and mitigated the SEU effect for FSM. Those methods were used and evaluated in XX_1 satellite ’s FPGA design, which were proved effective.
finite state machine FPGA SEU synthesis
Liu Yuan Sun Zhao-wei Zhao Dan
ISSCAA 2008 Research Center of Satellite Technology,Harbin Institute of Technology,Harbin 150001,China
国际会议
深圳
英文
143-146
2008-12-10(万方平台首次上网日期,不代表论文的发表时间)