FPGA On-Board Computer design based on Hierarchical Fault tolerance
Safety is a crucial requirement of On-Board Computer (OBC) design of a satellite, especially for the new type OBC takes FPGA as central processor. Upon that this paper proposes a plan of FPGA OBC design and adds hierarchical fault tolerant concept to enhance the reliability of the OBC system. The fault tolerant architecture can be divided into three hierarchic ranks, containing single-CPU reconfiguration, component unit transfer and dual-CPU subrogation. One of the above fault manage mode will be chosen to deal with problems according to error situation in-orbit. In the worst cases, all three modes may be used. The last part of the paper gives the functional verification approach under development for the hierarchical fault tolerant OBC design.
Lei Xing Zhaowei Sun Guodong Xu
Research Center of Satellite Technology,Harbin Institute of Technology Harbin 150001,China
国际会议
深圳
英文
1339-1343
2008-12-10(万方平台首次上网日期,不代表论文的发表时间)