MBIST design and implementation of a H.264/AVC video decoder chip

摘要：

This paper implemented MBIST in a H.264/AVC video decoder chip, Neptune. Neptune has 1.5 million gates, 37 memory blocks_ In need of testing, a complete design for test should be done. This paper mainly designed and implemented Memory BIST targeting the 34 RAM block, except the 3 ROM blocks. The design included building design flow, choosing algorithm, generating background data and BIST controller integration. By BIST controller reuse, circuit area was saved. Working mode simulation, test time analysis, fault coverage analysis, circuit performance evaluation were done. The result showed that the MBJST achieved 100％ fault coverage by a 2.4go/ increase in chip area.

关键词： H.264/A VC BIST fault covenzge

作者: Ligang HOU Wuchen WU Jiahui Zhu

作者单位: VLSI &System Lab Beijing University of Technology Beijing, China HSC-DAC Dept.Analog Devices Inc.Beijing Design Center Beijing, China

会议类型: 国际会议

会议名称: 2010 2nd International Conference on Signal Processing System(2010年信号处理系统国际会议 ICSPS 2010)

会议地点: 大连

会议语种:英文

页码: 87-90

在线出版日期: 2010-07-05（万方平台首次上网日期，不代表论文的发表时间）