The applicaiton of Calculus on Runtime Verification

摘要：

In this paper, a uniform calculus-based approach for synthesizing monitors checking correctness properties specified by a large variety of logics at runtime is provided, including future and past time logics, interval logics, state machine and parameterized temporal logics. We present a calculus mechanism to synthesize monitors from the logical specification for the incremental analysis of execution traces during test and real run. The monitor detects both good and bad prefix of a particular kind, namely those that are informative for the property under investigation. We elaborate the procedure of calculus as monitors.

关键词： Calculus Runtime Verification synthesizing monitors

作者: Ruiyun Xie Benzhai Hai Zuhua Guo Mingzhu Shao

作者单位: Computer Science &Technology Henan Mechanical and Electrical Engineering College Xinxiang China Computer Science &Technology Henan Normal University Xinxiang China

会议类型: 国际会议

会议名称: 2010 2nd International Conference on Signal Processing System(2010年信号处理系统国际会议 ICSPS 2010)

会议地点: 大连

会议语种:英文

页码: 1073-1077

在线出版日期: 2010-07-05（万方平台首次上网日期，不代表论文的发表时间）