RC-Cache: Soft Error Mitigation Techniques for Low-Leakage On-Chip Caches

摘要：

This paper presents a kind of reliable low-leakage cache - RC-Cache, to solve the problem of high soft error rate in low-leakage on-chip caches. The proposed structure combines circuit technique and micro-architecture technique, and can reduce impacts of soft errors on leakage power optimization technique of caches. At circuit level, we improve the soft error immune of SRAM through specially designed soft error immune SRAM cell - SI-SRAM; at micro architecture level, we reduce the soft error vulnerability of low-leakage caches by burst-based access prediction and early write-back operation. Experimental results show that in normal mode, soft error rate of RC-Cache is only 1/7 of the conventional cache, and in drowsy mode it is just 2/5. The techniques significantly improve the reliability of cacbes and, to a certain extent, mitigate soft error problem of low-leakage on-chip caches.

关键词： soft error drowsy cache leakage SRAM reliability low-power

作者: Yan Sun Minxuan Zhang Shaoqing Li Chao Song Yali Zhao

作者单位: School of Computer National University of Defense Technology Changsha 410073, China

会议类型: 国际会议

会议名称: 2010 2nd International Conference on Signal Processing System(2010年信号处理系统国际会议 ICSPS 2010)

会议地点: 大连

会议语种:英文

页码: 1690-1694

在线出版日期: 2010-07-05（万方平台首次上网日期，不代表论文的发表时间）