Design of a Novel Adaptive FIR Filter Based on FPGA

摘要：

In this paper, the design of adaptive FIR digital filter is studied and a novel implementations of adaptive FIR filter based on multiplier-free structure is proposed. The implementation scheme based on the distributed algorithm uses access to a range of look-up table(LUT) to replace the traditional method of multiply-accumulate operations. The update of the adaptive filter weights is based on the quantization error least mean square algorithm(QE-LMS). To reduce the time, the update process of the LUT which stored filter weights is realized by a novel LUT update using a matched auxiliary LUT. The filter is described with VHDL, and realized on Cyclone series chip. The system simulation and timing analysis show that the proposed method can implement FIR filters with the smaller resource usage and higher speed.

关键词： adaptive filter distributed algorithm least mean square algorithm FPGA

作者: Zhang Bo Tian Xiuwei

作者单位: College of Computer and Information Engineering,Tianjin Normal University,Tianjin 300074,China

会议类型: 国际会议

会议名称: 2011 10th International Conference on Electronic Measurement & Instruments(第十届电子测量与仪器国际会议 ICEMI2011)

会议地点: 成都

会议语种:英文

页码: 68-70

在线出版日期: 2011-08-16（万方平台首次上网日期，不代表论文的发表时间）