An SOPC Test Strategy Based on wrapper/TAM co-optimization
Recently, system-on-a-Programmable-Chip (SOPC) has become more and more popular. However, prior research only concentrated on System on Chip (SoC) test problem. In this paper, we address the SOPC test problem. An SOPC test strategy has been proposed to solve the wrapper/TAM co-optimization problem for the SOPC. Our wrapper design algorithm is proposed on earlier approach by arranging the internal scan chains scientifically to archive lower testing time. Then we present a new test schedule technique, in which the testing time for each IP cores are calculated by our wrapper design algorithm. Experimental results are present for ITC02 test benchmark as well as Integrated Processor.
SOPC wrapper design test schedule.
Yu Yang Chen Yefu Peng Yu
Dept. of Automatic Test and Control,Harbin Institute of Technology Harbin,Heilongjinag 150001,China
国际会议
2011 10th International Conference on Electronic Measurement & Instruments(第十届电子测量与仪器国际会议 ICEMI2011)
成都
英文
680-684
2011-08-16(万方平台首次上网日期,不代表论文的发表时间)