Performance investigation of a 1-bit periodic sigma delta phase-signal generator for mixed-signal embedded test

摘要：

In this paper we present an implementation and performance investigation of a phase signal generator for use in mixed-signal embedded test. The generator consists of a circular 1xN-bit memory and a time-mode filter. The memory is loaded with a phase-modulated sigma-delta encoded bit stream generated in software. Due to its digital nature, the generator except for the time-mode filter is fully synthesizable using standard logic. A discrete prototype was constructed using offthe shelf components at 50 MHz. It shown that the phase of the reference clock frequency can be shifted by approximately 45 degrees with a phase step of about 1 degree. The main limitation of this approach lies with the phase noise associated with the PLL making up time-mode filter.

关键词： Design-For-Test Built-In-Self-Test Automatic Test Equipmewnt PLL Phase Signal Generator Embedded Test

作者: Azhar Ahmed Chowdhury Gordon W Roberts

作者单位: Integrated Microsystems Laboratory,McGill University3480 University Street,Montreal,Quebec,CANADA H3A 2A7

会议类型: 国际会议

会议名称: 2011 10th International Conference on Electronic Measurement & Instruments(第十届电子测量与仪器国际会议 ICEMI2011)

会议地点: 成都

会议语种:英文

页码: 731-737

在线出版日期: 2011-08-16（万方平台首次上网日期，不代表论文的发表时间）