Design and FPGA Implementation of Linear FIR Low-pass Filter Based on Kaiser Window Function

摘要：

Aiming at the requirements of real time signal processing, a cut-off frequency of 100 KHz, 16-tap direct form FIR linear-phase low-pass filter using Kaiser Window function was designed out based on DSP Builder system modeling approach. The signal waveforms in time domain and frequency domain before and after filtering were analyzed. Ultimately, a highest response frequency of 61.71MHz high-speed FIR low-pass filter was implemented on EP2C35F672C8 FPGA. Design efficiency and filter performance has been greatly improved.

关键词： FIR FPGA Low-pass fiber DSP Builder Kaiser window

作者: GAO Jinding HOU Yubao SU Long

作者单位: Central South University, Changsha, Hunan, 410083, China Hunan International Economics University, C Hunan International Economics University, Changsha, Hunan, 410205, China

会议类型: 国际会议

会议名称: 2011 Fourth International Conference on Intelligent Computation Technology and Automation(2011年第四届智能计算技术与自动化国际会议 ICICTA 2011)

会议地点: 深圳

会议语种:英文

页码: 496-498

在线出版日期: 2011-03-28（万方平台首次上网日期，不代表论文的发表时间）