A phase-locked loop with static phase error calibration

摘要：

A phase-locked loop (PLL) with static phase error calibration is presented. A current-mismatch adjusting circuit is aid to reduce the current mismatch of charge pump. The current mismatch is induces a phase error in the PLL. The proposed circuit is simulated in a 0.35um CMOS process with 3.3V supply voltage. The measured static phase error without and with current-mismatch adjusting circuit is 65.41ps and 3.44ps, respectively.

关键词： current-mismatch charge-pump phase-locked loop(PLL)

作者: Po-Tsun Wu Shao-Ku Kao

作者单位: Department of Electrical Engineering and Green Technology Research center, Chang Gung University Tao-Yuan, Taiwan, R.O.C.

会议类型: 国际会议

会议名称: 2010 International Conference on Circuit and Signal Processing(2010年电路与信号处理国际会议 ICCSP 2010)

会议地点: 上海

会议语种:英文

页码: 80-83

在线出版日期: 2010-12-25（万方平台首次上网日期，不代表论文的发表时间）