Cache Performance Research For Embedded Processors

摘要：

The embedded processor performance is significantly influenced by cache whose performance depend on its architecture parameters. Meanwhile, In order to overcome the non-timing accurate flaw of software simulation method, In this paper, a hardware emulation method —RTL level models is used for CPU and cache controller, while circuit model for cache memory cell—is adopted to do research on cache performance. A more accurate design space, miss rate and cycle trend influenced by cache parameters, is presented. Compared with Round Robin, it shows that miss rate and cycle number of instruction cache is reduced by 22.08％ and 20.36％, respectively, because Pseudo-LRV is adopted.

关键词： cache performance research hardware model replacement algorithm

作者: Chenxu WANG Jiamin ZHENG Mingyan YU

作者单位: Microelectronics Center Harbin Institute of Technology at Weihai Weihai, Shandong

会议类型: 国际会议

会议名称: 2010 International Conference on Circuit and Signal Processing(2010年电路与信号处理国际会议 ICCSP 2010)

会议地点: 上海

会议语种:英文

页码: 95-98

在线出版日期: 2010-12-25（万方平台首次上网日期，不代表论文的发表时间）