A FPGA Based Reconflgurable Uniform Random Number Generator
Random Number Generators (RNG) are widely used in image and signal processing applications. In this paper, a reconflgurable hardware architecture of Combined Tausworthe RNG is proposed. The output bitwidth and the period of the proposed RNG are reconflgurable. A matrix based leap ahead structure to implement the Transform Module is introduced here. Four different RNGs based on the proposed architecture are implemented on Xilinx Vertex 4 FPGA. The 32-bit and 64-bit RNGs occupies only 55 and 147 slices and acquires a clock frequency as high as 991 MHz. The throughputs accordingly are 31.7×10~9 and 63.4 ×10~9 bits per second. These are 3 times and 6 times more than that of MT 19947 and TT800.The throughputs per slice of them are 576×10~6 and 434 ×10~6 bits per slice per second. These are 5 times more than that of TT800 and 50 times more than that of MT19937. The quality of the generated random numbers are tested by DIEHARD and TEST U01 CRUSH.
Reconflgurable Computing Hardware Accelerator Random Number Generator FPGA
GU Xiao-chen JIANG Jiang ZHANG Min-xuan
PDL,School of Computer National University of Defense Technology Changsha, China, 410073
国际会议
秦皇岛
英文
450-455
2010-11-05（万方平台首次上网日期，不代表论文的发表时间）