A Dual-Threshold Scheme for Clocked Adiabatic Logic Circuits

摘要：

With scaling down in future technologies, the leakage current of transistors is becoming an increasingly large component in the total power dissipations of integrated circuits. This paper presents a dualthreshold voltage technology of improved CAL circuits for reducing leakage power dissipations while still maintaining high performance. An ISCAS cl7 benchmark circuit from the ISCAS 85 combinational benchmark set is verified using the dual-threshold voltage technique. All circuits are simulated using NCSU-Free PDK-1.3 45nm CMOS processes by HSPICE simulations. The results show that the ISCAS cl7 benchmark circuit with dual-threshold voltage technique not only can reduce the total power dissipation, but also can reduce the leakage dissipation largely.

关键词： nanometer circuits adiabatic computing dual threshold technique leakage reduction

作者: Haiyan Ni Li Su Jianping Hu

作者单位: Faculty of Information Science and Technology Ningbo University Ningbo City 315211,China

会议类型: 国际会议

会议名称: 2010 4th International Conference on Intelligent Information Techonlogy Application(第四届智能信息技术应用国际学术研讨会 IITA 2010)

会议地点: 秦皇岛

会议语种:英文

页码: 503-506

在线出版日期: 2010-11-05（万方平台首次上网日期，不代表论文的发表时间）