P-type Complementary Pass-Transistor Adiabatic Logic with Dual-Threshold CMOS Technique
Reduction in leakage dissipations has become an important concern in low power and high performance applications. DTCMOS (Dual-threshold CMOS) has been proven as an effective way to reduce sub-threshold leakage consumption. P-type logic circuits that consist mostly of PMOS transistors can significantly reduce the gate leakage dissipations in CMOS processes with gate oxide structure. In this paper, a dual-threshold CMOS (DTCMOS) scheme for P-type CPAL (complementary pass-transistor adiabatic logic) circuits is addressed. A full adder is verified using the DTCMOS P-type CPAL circuits. All circuits are verified with HSPICE using the 65nm CMOS process with gate oxide materials. The P-type CPAL circuits using DTCMOS (dual threshold CMOS) technique exhibit large energy savings, since both sub-threshold and gate leakage dissipations are reduced effetely.
Adiabatic computing P-type circuits Dual threshold technique Leakage reduction
Haiyan Ni Lifang Ye Jianping Hu
Faculty of Information Science and Technology Ningbo University Ningbo City 315211, China
国际会议
秦皇岛
英文
507-510
2010-11-05（万方平台首次上网日期，不代表论文的发表时间）