The Study on Nano-Electromechanical Transistors using Atomic Layer Deposition
The process presented here is CMOS compatible just, but low-temperature, thus residual stress effects have no significant influence on device performance, furthermore the process is unique in its ability to create n-terminal devices with n-different gap heights, with 3-terminal device having 2 different gap heights presented here. The process is relatively simple, allowing for the fabrication of embedded electrodes, and associated sacrificial layers with one e-beam write, RIE step, deposition step, and lift-off per electrode. The NEMS transistors introduced here represent the fundamental building blocks of nano-mechanical logic devices and subsequent computing architectures. The development of the devices reported here immediately allows for the creation of mechanical logic gates, because fundamental logic gates, analogous to CMOS inverters, can be constructed by combining complimentary biased 3-terminal switches.
Nano-Electromechanical Transistors Atomic Layer Deposition
Zhao Lingya Wang Yingjian Zhigang Ji
Langfang Polytechnic Institute Langfang teachers college Hebei University of Engineering, Handan, China
国际会议
北京
英文
62-65
2010-09-18（万方平台首次上网日期，不代表论文的发表时间）