The Implementation of High-speed FFT processor based on FPGA

摘要：

A method of implementing 256-point, high-speed and 16-bit complex FFT is presented on the radix-4 FFT algorithm. By using a fixed geometry addressing, pipeline designing and block floating point structure, the data has the greater precision and dynamic range. The results show that the design is efficient, strongly extensive and occupies less resource. It is a good method to meet the high-speed digital signal processing requirements.

关键词： fixed geometry pipeline block floating point high speed FFT processor.

作者: LI Xiao-feng Chen Longv Wang Shihu

作者单位: Department of Electromechanical Engineering Beijing Institute of Technology. Beijing,China

会议类型: 国际会议

会议名称: 2010 International Conference on Computer,Mechatronics,Control and Electronic Engineering(2010计算机、机电、控制与电子工程国际会议 CMCE 2010)

会议地点: 长春

会议语种:英文

页码: 236-239

在线出版日期: 2010-08-24（万方平台首次上网日期，不代表论文的发表时间）