Design of a 10-bit, 50MSPS PipeUne CMOS ADC

摘要：

Based on the principle of Pipeline ADC, a 10-bit, 50-MS/s pipeline All converter is presented in this paper. Combining wttb bootstrap circuit and bottom-plate sampling technology, a high linearity on-chip sample-and-hold (S/H) is realized. This ADC is optimized for high static and dynamic performance applications in imaging and digital communications. It operates at 1.2V power supply and achieves a power dissipation of 36 mW at typical case. The simulation results show that this ADC achieves over 56dB spurious-free dynamic range (SFDR) and 54DB SINAD. The prototype design is of 10-bit pipeline ADC is fabricated in 0.13μm CMOS standard miwd-signal process, and the IP core occupies an area of 0.52mm2.

关键词： ADC Pipeline Comparator Bootstrap

作者: PEI Xiaomin SONG Lixin

作者单位: XiangFan University Xiangfau,CHN XiangFan University Xiangfan,CHN

会议类型: 国际会议

会议名称: 2010 International Conference on Computer,Mechatronics,Control and Electronic Engineering(2010计算机、机电、控制与电子工程国际会议 CMCE 2010)

会议地点: 长春

会议语种:英文

页码: 41-44

在线出版日期: 2010-08-24（万方平台首次上网日期，不代表论文的发表时间）