THE DESIGN OF A RSSI FOR THE GPS RECEIVER

摘要：

This paper describes CMOS circuit design techniques for a limiting amplifier and received signal strength indicator (RSSI) circuits for the GPS receiver. The circuits in limiting amplifier and RSSI are all preudo differential to minimize the requirement of the supply voltage and be prepared against device mismatch. A folded diode load and folded cascade structure gain cell is introduced for each gain cell of the amplifier. The architecture of the offset subtracter is a cross-connected sourcecoupled pair. Based on SMIC 0.18um CMOS Technology with a 1.8 V supply, the RSSI provides 55 dB of loglinear range with less than 1.5dB error due to process variation. The overall power consumption is 3.7m W.

关键词： CMOS analog integrated circuit limiting amplifier RSSI GPS Receiver

作者: Yang Sun Xiaolin Zhang Wenbo Xia

作者单位: Electronic and Information Engineering Beihang University Beijing,P. R. China

会议类型: 国际会议

会议名称: 2010 International Conference on Computer,Mechatronics,Control and Electronic Engineering(2010计算机、机电、控制与电子工程国际会议 CMCE 2010)

会议地点: 长春

会议语种:英文

页码: 219-222

在线出版日期: 2010-08-24（万方平台首次上网日期，不代表论文的发表时间）