Improved Design Of The Multiplier In The Digital Filter

摘要：

This paper presents an improved hardware design of multiplier in digital filter utilizing Canonical Signed Digit and Horners scheme. Two multiplier structures, a cascaded adder structure and accumulative structure, have been discussed. Both could be used in multiplier implementation, while they occupied different silicon resource in different conditions. By comparing both the structures, the area optimization methodology is found out which can decrease about 10.19％ of the total area of whole module.

关键词： CSD format multiplier digital signal processor digital filters logic design

作者: Xiaolin Yuan Tang Ying Guo Chunpeng

作者单位: Infineon Technologies, Xian, 710075, China College of Optical and lectronic Technology, China Jiliang University, Hangzhou, 310018

会议类型: 国际会议

会议名称: 2010 International Conference on Computer and Communication Technologies in Agriculture Engineering(计算机与通信技术在农业工程国际会议 CCTAE 2010)

会议地点: 成都

会议语种:英文

页码: 13-16

在线出版日期: 2010-06-12（万方平台首次上网日期，不代表论文的发表时间）