Design and Implementation of HDLC Protocol and Manchester encoding based on FPGA in Train Communication Network

摘要：

This article has designed a set of train communication network link layer and physical layer implementations. The program uses a top-down design method developed the FPGA and the ARM as the core of the circuit diagrams. The data between two pairs transmit by a dual-FIFO. By analyzing the existing implementation HDLC Protocol approach proposed HDLC protocol implementations using FPGA. And the use of FPGA on-chip all-digital phase-locked loop to extract the bit synchronous clock to achieve the Manchester encoding and decoding. In the finished making the actual PCB for the actual test, the results have verified the accuracy and reliability of the design.

关键词： FPGA HDLC Manchester Code DPLL Bit Synchronous

作者: Guozheng Li Nanlin Tan

作者单位: State Key Laboratory of Rail Traffic Control and Safety Beijing Jiaotong University, China

会议类型: 国际会议

会议名称: Third International Conference on Information and Computing(第三届信息与计算科学国际会议 ICIC 2010)

会议地点: 无锡

会议语种:英文

页码: 105-108

在线出版日期: 2010-06-04（万方平台首次上网日期，不代表论文的发表时间）