Overview of Inter-communication Mechanism on Multi-core Processor

摘要：

As the increasing in chip density, on-chip communication will be a key factor in determining the performance and power consumption of the multi-core processor. Some typical communication mechanisms of the multi-core processor at present are introduced in detail in this paper, such as cache-shared bus structure, shared-bus structure and NoC-based structure, and there advantages, disadvantages and ranges of application are also analyzed. Finally, the basic architecture and research of the NoC are presented in particularly, and its advantages are also analyzed, such as scalability, reusability and predictability. NoC is inevitable choice to meet the high level of integration chips.

关键词： multi-core processor on-chip communication interconnect technology NoC

作者: XingangJu Yi Qin LiangYang ShitanHuang

作者单位: Xian Microelectronics Technology Institute Xian China

会议类型: 国际会议

会议名称: The 2010 International Conference on Computer Application and System Modeling(2010计算机应用与系统建模国际会议 ICCASM 2010)

会议地点: 太原

会议语种:英文

页码: 187-190

在线出版日期: 2010-10-22（万方平台首次上网日期，不代表论文的发表时间）