A leakage Current Limited Robust SRAM for Subthreshold/Nearthreshold Applications

摘要：

In this paper, a leakage current limited SRAM bitcell operating in subthreshold/nearthreshold region is demonstrated in IBM 0.13 urn CMOS process. Proposed bitcell exhibits wide hysteresis effect, making the design less vulnerable to process variation. Its hold margin is 30.2％ and 18.9％ greater than conventional 6T SRAM and referenced SRAM (at 400 mV). At the same times, the SRAM trip point voltage changes according to bitline voltages. Its read margin is 45％ and 9％ greater than conventional 6T SRAM and referenced SRAM (at 400 mV). Dynamic leakage cut off transistor is utilized to reduce leakage current without inducing dynamic energy penalty. Thus, compared to the referenced 4kb SRAM array, proposed array optimum-energy supply voltage is scaled from 400 mV to 310 mV

关键词： subthreshold/nearthreshold SRAM low leakage current static noise margin optimum-energy supply voltage

作者: Yang Tongmu

作者单位: Nanjing Branch, Shanghai Baosight Software Co.,Ltd.College of Software Engineering, Southeast University Nanjing, China

会议类型: 国际会议

会议名称: The 2010 International Conference on Computer Application and System Modeling(2010计算机应用与系统建模国际会议 ICCASM 2010)

会议地点: 太原

会议语种:英文

页码: 26-29

在线出版日期: 2010-10-22（万方平台首次上网日期，不代表论文的发表时间）