Input Buffer Planning for Network-on-Chip Router Design

摘要：

System-on-Chip(SoC) designs become more complex nowadays. The communication between processing elements are suffering challenges due to the wiring problem. Networks-on-Chip(NoC) approach was proposed as a promising solution. Buffers are one of the major resources used by the routers. In this paper, an application-specific buffer planning approach that can be used to customize the router design in networks-on-chip(NoC) is presented. More precisely, given the mapping of the target application and the traffic characteristics, the approach can automatically assign the buffer depth for each input channel in different routers across the chip. The experimental results show that the system buffering resources can be utilized more effectively. In contrast with the uniform buffer allocation, about 50％ saving in buffering resources can be achieved by automatic buffer allocation using our approach without any reduction in performance.1

关键词： SoC NoC buffer allocation traffic characteristic

作者: Yarning Yin Shuming Chen Xiao Hu

作者单位: Department of Computer Science and Technology National University of Defense Technology Changsha, China

会议类型: 国际会议

会议名称: The 2010 International Conference on Computer Application and System Modeling(2010计算机应用与系统建模国际会议 ICCASM 2010)

会议地点: 太原

会议语种:英文

页码: 201-204

在线出版日期: 2010-10-22（万方平台首次上网日期，不代表论文的发表时间）