Design of PLC Timer System Based on FPGA

摘要：

Aiming at the design of the small PLC timer system, based on the analysis of operational characteristics of PLC timer and the process of PLC user timer program and the data transmission requirements of PLC user program execution module and the timer, a method which applies the FPGA Parallel algorithm to designing small PLC timer system, is presented. The timer system is composed of clock generator unit, timing unit, timing control unit and the chip select circuit. While the timer runs at the speed of lms timed pulse, the operation of timer is translated into the operation of RAM memory cell which is made up of FPGA. That makes user can operate on RAM memory cell instead of the timer, and it just take up a few execution time of PLC user program. This paper introduces the theory and structure of the FPGA timer system, the state transition diagram of timer control module, the timing diagram of user program execution module operating on timer, finally take an experiment and gives analysis of the results.

关键词： PLC timer system FPGA dynamic information code parallel operation state transition

作者: Li Kejian Liu Tong Cai Qizhong Yu Ling

作者单位: School of Electronic Information and Control Eng Guangxi University of Technology Liuzhou Guangxi Ch Library Lushan College of Guangxi University of Technology Liuzhou Guangxi China

会议类型: 国际会议

会议名称: The 2010 International Conference on Computer Application and System Modeling(2010计算机应用与系统建模国际会议 ICCASM 2010)

会议地点: 太原

会议语种:英文

页码: 197-201

在线出版日期: 2010-10-22（万方平台首次上网日期，不代表论文的发表时间）