A Network-on-Chip Emulation Framework for OFDM System Based on FPGAs
In the field of integrated circuit design, the on-chip communications for parallel computations are increased rapidly. Due to the low efficiency of the traditional bus-based structure of System-on-Chip (SoC), Networks-on-Chip (NoC) is emerging as a predominant substitute for interconnection in SoC. Meanwhile, Orthogonal Frequency Division Multiplexing (OFDM) technique has becoming a popular research topic in the thriving wireless mobile communication area. This paper proposes how to implement OFDM system on a NoC platform, which is composed by 4×4 2-D mesh tiles in Xilinx Virtex-TV FPGA arrays. Worm hole switching, deterministic routing and Virtual Output Queuing (VOQ) mechanism are adopted in the switch and router design. All Processing Elements (Pes) are homogeneous, and implemented by PowerPC cores embedded within the Xilinx Virtex-Ⅳ FPGAs. In addition, a network interface (NI) has been designed to control the data transactions between switching node and PE. Our experiment proves the Network on Chip emulation framework for OFDM system.
networks on chip OFDM network interface FPGA powerpc
Jianrong Wang Xiang Ling Yiou Chen
National Key Lab of Science and Technology on Communications University of Electronic Science and Technology of China Chengdu, Sichuan, P.R.China, 611731
国际会议
太原
英文
413-417
2010-10-22（万方平台首次上网日期，不代表论文的发表时间）