Study on Integral-limits for Estimating High-stability-clocks Jitter

摘要：

Power-law-integral is one normal conversion formula to indirectly estimate sub-picosecond-level clock jitter, but its result depended by the integral-upper-limit and lower-limit. How to choose integral limits are the key problem to use this formula for more reasonable. This paper introduces clock jitter in time domain and frequency domain, clocks phase noise characteristics, and from phase noise into jitter formula. Analysis the relationship between power-law integral lower limit and clock signal frequency, A/D conversion resolution, etc., proposed a formula to estimate the limit. To upper limit, comparative analysis of the quantization noise power spectral density and clock signals phase noise power spectral density, the choosing up-iimit reference principle.

关键词： jitter phase nois power-law-integral integral limits

作者: Cao Peng Luo Wen-qiu Meng Fan-jun Wang Yan

作者单位: School of information and mechanical engineering Beijing Institute of Graphic Communication Beijing, Reconnaissance Intelligence and Equipment Institute Equipment Academy of Air Force Beijing, China

会议类型: 国际会议

会议名称: The 2010 International Conference on Computer Application and System Modeling(2010计算机应用与系统建模国际会议 ICCASM 2010)

会议地点: 太原

会议语种:英文

页码: 103-105

在线出版日期: 2010-10-22（万方平台首次上网日期，不代表论文的发表时间）