Hardware-Efficient Architecture for High Throughput Turbo Decoder

摘要：

In this paper, a hardware-efficient and high throughput Turbo decoder architecture is proposed, which employs the look-ahead structure to speed up the decoding processing. Furthermore, the proposed architecture employs smaller hardware area than the traditional method to compute the extrinsic information. The slide window method is adopted in the proposed architecture to reduce memory requirement. The proposed architecture can achieve a higher throughput ratio with a relatively low hardware cost.

关键词： turbo decoding look-ahead slide window logMAP

作者: Jienan Chen Jianhao Hu

作者单位: Dept.of National Key Laboratory of Science and Technology and Technology on Communications University of Electronic Science and Technology of China Chengdu, China

会议类型: 国际会议

会议名称: The 2010 International Conference on Computer Application and System Modeling(2010计算机应用与系统建模国际会议 ICCASM 2010)

会议地点: 太原

会议语种:英文

页码: 207-211

在线出版日期: 2010-10-22（万方平台首次上网日期，不代表论文的发表时间）