A Programmable High-speed Pulse Swallow Divide-by-N Frequency Divider For PLL Frequency Synthesizer
The implementation of a high-speed pulse swallow frequency divider for a PLL (Phase Locked Loop) frequency synthesizer, using a 0.18μm CMOS technology and operating with a 1.8V power supply, is described. The frequency divider is used as a scalable programmable divide-by-N frequency divider. It employs a divide-by-8/9 dual-modulus prescaler, two programmable counters, and a control circuit necessary for the time sequence and operation of the division. In the pulse swallow frequency divider, the divider circuit is attractive for the large range of programmable divide ratio from 120 to 400 since the architecture is based on using an original design of D-type Flip-Flop (DFF) with synchronous number-set and clear. Post-simulated results show that the programmable dividers operation frequency is from 0.75 GHz to 2.2 GHz with steep pulse output wave-form, providing a stable clock edge of the required frequency for the PLL frequency synthesizer.
pulse swallow frequency divider the large range of programmable divide ratio original design of D-type flip-flop PLL
Zhiqiang Gao Yuanxu Xu Peng Sun Enyi Yao Yongshuang Hu
Department of Electronic Information Science and Technology Harbin Institute of Technology Harbin, Heilongjiang 150001, China
国际会议
太原
英文
315-318
2010-10-22（万方平台首次上网日期，不代表论文的发表时间）