An Interconnect Model for Storage Array on Chip
In this paper, a model of transmission line based on Laplace transform is presented;this model could be computed repeatedly used by second or more-order frequency function, in which a signal of voltage difference between stimulus and response is proposed. It is possible to calculate iterative discrete convolution with computer instead of analytic continuous convolution, because the mentioned voltage signal reach to zero when the time variation reach to infinity. The model could be used in delay specificity analysis in large-scale storage array. The model is more approaching to physical analysis and HSPICE simulation results than traditional Elmore model.
Interconnect model Delay of storage array Computer aided design
Wang Tianran Xing Zuocheng Huang Ping Fu Guitao Ma Anguo
School of Computer National University of Defense Technology ChangSha,Hunan,China
国际会议
昆明
英文
192-197
2010-10-17（万方平台首次上网日期，不代表论文的发表时间）